こまちチラ裏

信号線のまとめ方

これはべんり

typedef.vhd

subtype signal is std_logic_vector(31 downto 0); --信号幅
type signal_array_t is array (0 to 10) of signal; --本数

component.vhd

use work.typedef.vhd;

entity cmponent_hoge is
port(
    signal_arr : inout signal_array_t
)
end entity